The present invention relates to a layout design method, and more particularly to a layout design method for a semiconductor device having a multilevel interconnection structure using metal interconnections.
In processes for forming metal interconnections such as aluminum interconnections for a semiconductor device, a plasma etching technique has widely been used for patterning an interconnection layer. In the plasma etching process, charges are generated in the interconnection. FIG. 1 is a fragmentary circuit diagram illustrative of a route extending between first and second inverters to explain an antenna effect. FIG. 2 is a fragmentary cross sectional elevation view illustrative of a first type route extending between first and second inverters in a semiconductor substrate to explain an antenna effect. FIG. 3 is a fragmentary cross sectional elevation view illustrative of a second type route extending between first and second inverters in a semiconductor substrate to explain an antenna effect.
With reference to FIG. 1, a route 50 extends between a first inverter 51 and a second inverter 52. The first inverter 51 comprises a series connection of a first p-channel MOS field effect transistor PMOS1 and a first n-channel MOS field effect transistor NMOS1 between a high voltage line and a ground line. The first inverter 52 comprises a series connection of a second p-channel MOS field effect transistor PMOS2 and a second n-channel MOS field effect transistor NMOS2 between a high voltage line and a ground line.
With reference to FIG. 2, the route 50 comprises an interconnection 111a. The interconnection 111a has a first end connected through a diffusion contact 4 to one of diffusion regions of the first n-channel MOS field effect transistor NMOS1 which is formed in a semiconductor substrate 10. The interconnection 111a has a second end connected through a gate contact 5 to a gate electrode on a gate insulating film of a second n-channel MOS field effect transistor NMOS2 which is formed in the semiconductor substrate 10. If the charges are generated in the interconnection 111a, then the charges are moved through the diffusion contact 4 and the diffusion region 1 to the substrate 10. No charge accumulation thus appears in the interconnection 111a. 
With reference to FIG. 3, the route 50 comprises first level interconnections 111b and 111c, and a second level interconnection 121. A first end of the second level interconnection 121 is connected through a first through hole 116a to the first level interconnection 111b. A second end of the second level interconnection 121 is connected through a second through hole 116b to the first level interconnection 111c. The first level interconnection 111b is connected through a diffusion contact 4 to a diffusion region of the first n-channel MOS field effect transistor NMOS1 which is formed in a semiconductor substrate 10. The first level interconnection 111c is connected through a gate contact 5 to a gate electrode on a gate insulating film of a second n-channel MOS field effect transistor NMOS2 which is formed in the semiconductor substrate 10. When the first level interconnections 111b and 111c have just been formed, and the second level interconnection 121 has not yet been formed, the charges generated in the first level interconnection 111b flow through the diffusion contact 4 and the diffusion region 1 to the substrate 10. However, the charges generated in the first level interconnection 111c in the process for patterning the first level interconnection 111c are accumulated in the first level interconnection 111c, because the second level interconnection 121 has not yet been formed and thus the first level interconnection 111c has not yet been connected to the first level interconnection 111b. The first level interconnection 111c having the charge accumulation is, however, connected to the gate electrode 3 of each of the n-channel and p-channel MOS field effect transistors NMOS2 and PMOS2. The charge accumulation in the first level interconnection 111c varies the potential of the gate electrodes of the n-channel and p-channel MOS field effect transistors NMOS2 and PMOS2. If the potential of the gate electrodes of the n-channel and p-channel MOS field effect transistors NMOS2 and PMOS2 exceeds a threshold value which is determined by a thickness of the gate insulating film 2, then a breakdown appears in the gate insulating film 2. This effect is so called to as the antenna effect.
In accordance with the antenna effect, the increase in the amount of the accumulated charges in the gate electrodes 3 of the n-channel and p-channel MOS field effect transistors NMOS2 and PMOS2 increases the likelihood of breakdown of the gate insulating films 2.
FIG. 4 is a fragmentary cross sectional elevation view illustrative of a third type route extending between first and second inverters in a semiconductor substrate to explain an antenna effect. FIG. 5 is a fragmentary cross sectional elevation view illustrative of a fourth type route extending between first and second inverters in a semiconductor substrate to explain an antenna effect. Each of the third type route 50 and the fourth type routes 50 comprises a multilevel interconnection structure, wherein lower level interconnections connected to the gate electrodes are separated from the diffusion regions when the lower level interconnections are patterned by the plasma etching process. The charges are accumulated in the lower level interconnections connected to the gate electrodes but separated from the diffusion regions, whereby the gate potential varies to cause the above-described antenna effect. If the area in plan view of the lower level interconnections connected to the gate electrodes but separated from the diffusion regions is relatively large, a relatively large amount of charge is generated, whereby the antenna effect is remarkable. In order to solve the above problem with the antenna effect, it is effective to reduce the area of the lower level interconnections connected to the gate electrodes but separated from the diffusion regions.
A first conventional method of avoiding the antenna effect is disclosed in Japanese laid-open patent publication No. 11-214521. FIG. 6 is a fragmentary cross sectional elevation view illustrative of a fifth type route extending between first and second inverters in a semiconductor substrate to explain an antenna effect. In a minimum basic cell unit for automatic layout, immediately before gate input, any interconnections in the route are once separated to switch into the top level interconnection, whereby it is unnecessary to correct manually. This conventional method, however, causes the following problems. The disclosed conventional countermeasure to the antenna effect switches the individual basic cells in the automatic layout into the top level interconnection immediately before the input. The individual cells vary in size. The placement and routine may be made by use of the automatic layout tool. FIG. 7 is a diagram illustrative of a routine of interconnections to avoid switched regions in accordance with the conventional countermeasure to the antenna effect, wherein broken line represent interconnection and cross-hatched region represents the switched region in accordance with the conventional countermeasure to the antenna effect. The routine of interconnections are made to avoid the switched regions in accordance with the conventional countermeasure to the antenna effect, whereby the freedom in routine of interconnections is reduced. This further makes it possible to carry out a timing design in layout. Further, the layout area is increased to decrease the degree of integration, whereby the chip size is enlarged, and the cost performance is reduced.
In the above circumstances, it had been required to develop a novel layout design method free from the above problem.
Accordingly, it is an object of the present invention to provide a novel layout design method free from the above problems.
It is a further object of the present invention to provide a novel layout design method capable of suppressing antenna effect and also preventing reduction in freedom of routine of the interconnections.
It is a still further object of the present invention to provide a novel layout design method capable of making the timing design easy.
It is yet a farther object of the present invention to provide a novel layout design method allowing high density integration.
The present invention provides a layout design method for routine of a route comprising multilevel interconnections in a semiconductor device having at least a field effect transistor having a gate electrode, and the route extending between a diffusion region and the gate electrode, wherein each interconnection being connected to the gate electrode and being not connected to the diffusion region, when the each interconnection is patterned, has an area which does not exceed a predetermined reference value.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.